Integrated Circuits Research Articles

HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis

Modern integrated circuit (IC) design incorporates the usage of proprietary computer-aided design (CAD) software and integration of third-party hardware intellectual property (IP) cores. Subsequently, the fabrication process for the design takes place in untrustworthy offshore foundries that raises concerns regarding security and reliability. Hardware Trojans (HTs) are difficult to detect malicious modifications to IC that constitute a major threat, which if undetected prior to deployment, can lead to catastrophic functional failures or the unauthorized leakage of confidential information. Apart from the risks posed by rogue human agents, recent studies have shown that high-level synthesis (HLS) CAD software can serve as a potent attack vector for inserting Hardware Trojans (HTs). In this paper, we introduce a novel automated attack vector, which we term “HLS-IRT”, by inserting HT in the register transfer logic (RTL) description of circuits generated during a HLS based IC design flow, by directly modifying the compiler-generated intermediate representation (IR) corresponding to the design. We demonstrate the attack using a design and implementation flow based on the open-source Bambu HLS software and Xilinx FPGA, on several hardware accelerators spanning different application domains. Our results show that the resulting HTs are surreptitious and effective, while incurring minimal design overhead. We also propose a novel detection scheme for HLS-IRT, since existing techniques are found to be inadequate to detect the proposed HTs.

Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice

Due to the inclination towards a fab-less model of integrated circuit (IC) manufacturing, several untrusted entities get white-box access to the proprietary intellectual property (IP) blocks from diverse vendors. To this end, the untrusted entities pose security-breach threats in the form of piracy, cloning, and reverse-engineering, sometimes threatening national security. Hardware obfuscation is a prominent countermeasure against such issues. Obfuscation allows for preventing the usage of the IP blocks without authorization from the IP owners. Due to finite state machine (FSM) transformation-based hardware obfuscation, the design’s FSM gets transformed to make it difficult for an attacker to reverse-engineer the design. A secret key needs to be applied to make the FSM functional, thus preventing the usage of the IP for unintended purposes. Although several hardware obfuscation techniques have been proposed, due to the inability to analyze the techniques from the attackers’ standpoint, numerous vulnerabilities inherent to the obfuscation methods go undetected unless a true adversary discovers them. In this article, we present a collaborative approach between two entities—one acting as an attacker or red team and another as a defender or blue team , the first systematic approach to replicate the real attacker-defender scenario in the hardware security domain, which in return strengthens the FSM transformation-based obfuscation technique. The blue team transforms the underlying FSM of a gate-level netlist using state space obfuscation. The red team plays the role of an adversary or evaluator and tries to unlock the design by extracting the unlocking key or recovering the obfuscation circuitries. As the key outcome of this red team–blue team effort, a robust state space obfuscation methodology is evolved showing security promises.

A compact self-powered inductor-less piezoelectric energy harvesting circuit using gyrator

Abstract In traditional low-frequency energy harvesting circuits, a large matched inductor with a large size is unavoidable. To reduce the size of the circuit, this paper proposes a compact self-powered inductor-less high-efficiency piezoelectric energy harvesting circuit using a low-power-consumption gyrator. A self-powered floating gyrator inductor (FGI) is used in place of an inductor in the proposed circuit, and the required phasor response is acquired by using its voltage-current (V-I) relationship. The proposed circuit offers easy adjustability and performance benefits in small integrated circuits (IC) packages. The proposed circuit can be cost-effective and provide reduced area advantages in autonomous self-powered Internet-of-Things (IoT) and wireless sensor nodes (WSN) applications. Regarding harvested energy, the proposed circuit with a storage capacitor of 0.24F can obtain 320% improved performance than standard energy harvesting (SEH) along with the lowest power consumption of 0.25µW in self-powered operation. The proposed technique can also be applied to similar piezoelectric energy harvesting strategies with large inductors.

Quantum Machine Learning for Credit Scoring

This study investigates the integration of quantum circuits with classical neural networks for enhancing credit scoring for small- and medium-sized enterprises (SMEs). We introduce a hybrid quantum–classical model, focusing on the synergy between quantum and classical rather than comparing the performance of separate quantum and classical models. Our model incorporates a quantum layer into a traditional neural network, achieving notable reductions in training time. We apply this innovative framework to a binary classification task with a proprietary real-world classical credit default dataset for SMEs in Singapore. The results indicate that our hybrid model achieves efficient training, requiring significantly fewer epochs (350) compared to its classical counterpart (3500) for a similar predictive accuracy. However, we observed a decrease in performance when expanding the model beyond 12 qubits or when adding additional quantum classifier blocks. This paper also considers practical challenges faced when deploying such models on quantum simulators and actual quantum computers. Overall, our quantum–classical hybrid model for credit scoring reveals its potential in industry, despite encountering certain scalability limitations and practical challenges.

Algebraic side‐channel attacks on Trivium stream cipher

AbstractAlgebraic Side‐Channel Attacks (ASCAs), first proposed by Renauld and Standaert in 2009, are a potent cryptanalysis method against block ciphers. In this paper, the authors initially utilize ASCAs to analyze the security of the Trivium stream cipher, given its concise algebraic structure. Considering its efficiency in both hardware and software implementations, the authors deploy ASCAs to target Trivium implemented both in application specific integrated circuit (ASIC) under the Hamming Distance Leakage Model (HDLM) (noted as CASE 1) and in microcontrollers of various buses (i.e. some common 8‐bit, 16‐bit, and 32‐bit architectures, noted as CASE 2, CASE 3, and CASE 4, respectively) under the Hamming Weight Leakage Model (HWLM). Here, the authors’ attacks are conducted on power‐simulated targets and not on real devices. For a single power consumption trace without measurement errors, this paper presents experimental results using MiniSat 2.0. Unfortunately, the authors were unable to break the ASIC implementation of Trivium under HDLM (CASE 1) with a time complexity of 2109 s or so, which is worse than the exhaustive key attack. For CASEs 2 to 4, the authors can find the complete 288‐bit state of Trivium within a reasonable timeframe. Specially, the success rate can reach 100% with an average solving time of less than 1 s when only measuring the leakages of the first eight consecutive rounds for CASE 2. Furthermore, the authors can still successfully recover the internal state even when obtaining leakages of the first 41 rounds with a random loss rate. In fact, it can tolerate a 74% random loss rate for the first 223 rounds. With regard to the potential errors in the measurements, the authors mitigate them using Tolerant ASCA (TASCA). Similarly, CASE 1 cannot be compromised even in error‐free situations, while the authors can still successfully recover the internal state of CASEs 2 to 4 from a single power trace, even with a high error rate, including 100% incorrect measurements. Surprisingly, for CASEs 2 to 4, the authors can recover the internal state with a 100% success rate, regardless of the error rate. As a result, the security of Trivium will not be enhanced when transitioning from a smaller 8‐bit platform to a larger 32‐bit platform. In the end, the authors will consider some more abstract attack models. The results can provide us with additional insights into the security of Trivium from a different perspective.

Formation of Si nanopillars through partial sacrificing in super passivation reactive ion etching.

The vertical gate-all-around (VGAA) metal-oxide-semiconductor field-effect transistor (MOSFET) holds remarkable potential in the three-dimensional (3D) integrated circuits (ICs), primarily owing to its capacity for vertical integration. The Si nanopillar, a crucial channel in the VGAA MOSFET, is conventionally shaped via the reactive ion etching (RIE) system employing SF6/O2. Past studies have indicated that high O2 gas conditions in RIE often result in "Si grasses," irregular nanostructures, such as nanospikes on the bottom surface, due to over-passivation. However, this study revealed that ultrahigh O2 proportions (> 70%), especially when combined with low chamber pressure, inhibit the development of Si grasses in the RIE system (termed as super passivation). Nevertheless, this scenario leads to the segmentation of the Si nanopillar. To address this issue, a proposed partial sacrificing method, achieved by sacrificing the upper segment of the nanopillar through prolonged processing time and reduced mask size, successfully yielded Si nanopillars without Si grasses. Furthermore, an empirical model was developed to elucidate how experimental parameters influence etching characteristics, encompassing etching rate and Si nanopillar shape, through a systematic examination of the RIE etching process. This research significantly contributes to the production of VGAA MOSFETs and 3D ICs.&#xD.

All-optical 3D blue phase photonic crystal switch with photosensitive dopants

Blue phase (BP) liquid crystals (LC) have lately become the focus of extensive research due to their peculiar properties and structure. BPs exhibit a highly organized 3D structure with a lattice period in the hundreds of nm. Owing to such structure, BPs are regarded as 3D photonic crystals. The unique properties of this complex LC phase are achieved by the self-assembly of the LC molecules into periodic cubic structures, producing bright selective Bragg reflections. Novel applications involving 3D photonic crystals would certainly benefit from enhanced ground-breaking functionalities. However, the use of BPs as 3D has been traditionally curtailed by the BP crystals trend to grow as random polycrystals, making it difficult to develop practical BP-based photonic devices. The possibility of generating mm-sized BP monocrystals was recently demonstrated. However, besides increasing the scarce number of 3D photonic structural materials, their applications as 3D photonic crystals do not show apparent advantages over other solid materials or metamaterials. Having a tunable BP monocrystal, where crystals could be switched, modulating simultaneously some of their properties as 3D photonic crystals, they would constitute a new family of materials with superior performance to other existing materials, opening up a plethora of new applications. In this work, an all-optical switchable 3D photonic crystal based on BPs doped with tailored photoactive molecules is demonstrated. Two switching modes have been achieved, one where the BP reversibly transitions between two BP phases, BPI and BPII, (two different cubic crystal systems) while maintaining the monocrystallinity of the whole system. The second mode, again reversible, switches between BPI and isotropic state. None of these modes are related to the regular thermal transitions between LC phases; switching is triggered by light pulses of different wavelengths. This all-optical approach allows for a seamless fast remotely controlled optical switch between two 3D photonic crystals in different cubic crystal systems and between a photonic crystal and an isotropic matrix. Applications of switchable BPs for adaptive optics systems or photonic integrated circuits would make great advances using 3D photonic crystal switches. All-optical photonic systems such as these hold great promise for the development of tunable and efficient photonic devices such as dynamic optical filters and sensors, as they enable light-driven modulation and sensing applications with unprecedented versatility.

Development of flip-chip technology for the optical drive of superconducting circuits

We discuss the flip-chip mounting process of photodiodes and fiber sleeves on silicon substrates to meet the increasing demand for fabrication of highly integrated and hybrid quantum circuits for operation at cryogenic temperatures. To further increase the yield and success rate of the flip-chip procedure, the size of the gold stud bumps, and flip-chip parameters were optimized. Moreover, to connect optical fibers to the photodiodes in an optimal position, the fiber sleeves were aligned with specially fabricated alignment circles before applying thermocompression with the flip-chip machine. The mounted photodiodes were tested at both room temperature and cryogenic temperature, and we find that mechanical imperfections of the sleeve-ferrule combination limit the overall alignment accuracy. The experimental results show that our flip-chip process is very reliable and promising for various optical and electrical applications and, thus, paves the way for fabrication of hybrid chips, multi-chip modules and chip-on-chip solutions, which are operated at cryogenic temperatures.

The Genesis of AIbyAI Integrated Circuit: Where AI Creates AI

The typical Integrated Circuit (IC) development process commences with formulating specifications in natural language and subsequently proceeds to Register Transfer Level (RTL) implementation. RTL code is traditionally generated through manual efforts, using Hardware Description Languages (HDL) such as VHDL or Verilog. High-Level Synthesis (HLS), on the other hand, converts programming languages to HDL; these methods aim to streamline the engineering process, minimizing human effort and errors. Currently, Electronic Design Automation (EDA) algorithms have been improved with the use of AI, with new advancements in commercial (such as ChatGPT, Bard, among others) Large Language Models (LLM) and open-source tools presenting an opportunity to automate the chip design process. This paper centers on the creation of AIbyAI, a Convolutional Neural Network (CNN) IC entirely developed by an LLM (ChatGPT-4), and its manufacturing with the first fabricable open-source Process Design Kit (PDK), SKY130A. The challenges, opportunities, advantages, disadvantages, conversation flow, and workflow involved in CNN IC development are presented in this work, culminating in the manufacturing process of AIbyAI using a 130 nm technology, marking a groundbreaking achievement as possibly the world’s first CNN entirely written by AI for its IC manufacturing with a free PDK, being a benchmark for systems that can be generated today with LLMs.

Design and Test of Offset Quadrature Phase-Shift Keying Modulator with GF180MCU Open Source Process Design Kit

This article explores the evolution of integrated circuits (ICs), highlighting the fundamental role of open source Electronic Design Automation (EDA) tools in their development. It describes the IC’s design flow, differentiating between Front-end and Back-end design stages, and details the process of implementing the digital stage in offset quadrature phase-shift keying (OQPSK) modulation in an IC, including its hardware description language (HDL), the implementation test in the field-programmable gate array (FPGA), and the physical layout using the first manufactured open source process design kits (PDKs) in Global Foundries’ 180 nm, as well as the use of OpenLane and Caravel. To conclude, the results of the physical tests obtained from the digital modulation are presented, as well as the performance of the raised cosine shaping filter.

Formation of SiO2 thin films through plasma- enhanced chemical vapor deposition using SiH4/Ar/N2O

SiO2 films and their formation technologies are critical for the fabrication of Si-based integrated circuits (ICs). SiO2 films fabricated using plasma-enhanced chemical vapor deposition (PECVD) have become increasingly important because of the increasing trend of three-dimensional (3D) architectures in ICs. SiO2 films formed by PECVD have been widely studied for over 40 years; however, owing to the complex plasma reactions and the differences in system conditions, the relationship between the experimental parameters and film characteristics are disputed. In this study, focusing on the two important characteristics (surface morphology and deposition rate) of SiO2 films for 3 D ICs manufacturing, SiO2 film growth was systematically investigated via SiH4/Ar/N2O in PECVD; a theoretical reaction process model (including gas-phase reaction, chemical adsorption, and surface reaction) bridging the experimental parameters (chamber pressure, gas ratio, radio frequency power, and substrate temperature) and characteristics (surface morphology and deposition rate) of SiO2 films was established. This study contributes to the precise formation of sub-100 nanometer SiO2 films using PECVD for manufacturing 3 D ICs.

Multi-Objective Optimization in 3D Floorplanning

Three-dimensional integrated circuits can significantly mitigate the challenges posed by shrinking feature sizes and enable heterogeneous integration. This paper focuses on the 3D floorplanning problem. We formulate it as a multi-objective optimization issue and employ multi-objective simulated annealing to simultaneously optimize area, wirelength and number of vias. During the optimization process, neighboring solutions are explored in the design space through inter-layer or intra-layer perturbations, and decision criteria for the exploration process are formulated based on the dominance relationship of solutions. Test results on the GSRC benchmark demonstrate that our approach delivers superior performance in optimizing area and wirelength. Compared to 2D floorplanning, our method reduces the area by approximately 49% and the wirelength by 21%. Compared to other similar 3D floorplanning methods, we raise the success rate in satisfying the fixed-outline constraint to 100% and improve the wirelength by 3%. The multi-objective simulated annealing method proposed in this paper can effectively address the 3D floorplanning problem.

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

Adaptive Weighted Error-Correction Method Based on the Error Distribution Characteristics of Multi-Channel Alignment

As process nodes of advanced integrated circuits continue to decrease below 10 nm, the requirement for overlay accuracy is becoming stricter. The alignment sensor measures the position of the alignment mark relative to the wafer; thus, sub-nanometer alignment position accuracy is vital. The Phase Grating Alignment (PGA) method is widely used due to its high precision and stability. However, the alignment error caused by the mark asymmetry is the key obstacle preventing PGA technology from achieving sub-nanometer alignment accuracy. This error can be corrected using many methods, such as process verification and multi-channel weighted methods based on multi-diffraction, multi-wavelength and multi-polarization state alignment sensors. However, the mark asymmetry is unpredictable, complex and difficult to obtain in advance. In this case, the fixed-weight method cannot effectively reduce the alignment error. Therefore, an adaptive weighted method based on the error distribution characteristic of a multi-channel is proposed. Firstly, the simulation result proves that the error distribution characteristic of the multi-alignment result has a strong correlation with the mark asymmetry. Secondly, a concrete method of constructing weight values based on error distribution is described. We assume that the relationship between the weight value of each channel and the deviations of all channels’ results is second-order linear. Finally, without other prior process correction in the simulation experiment, the residual error’s Root Mean Square (RMS) of fixed weighted method is 14.0 nm, while the RMS of the adaptive weighted method is 0.01 nm, when dealing with five typical types of mark asymmetry. The adaptive weighted method exhibits a more stable error correction effect under unpredictable and complicated mark asymmetry.

Metatronics-inspired high-selectivity metasurface filter

Abstract Metatronic circuits extend the concept of subwavelength-scaled lumped circuitry from electronics to optics and photonics, providing a distinctive design paradigm for versatile optical nanocircuits. Here, based on the design of optical nanocircuits using metatronics concept, we introduce a general approach for dispersion synthesis with metasurface to achieve high-selectivity filtering response. We theoretically and numerically demonstrate how to achieve basic circuit lumped elements in metatronics by tailoring the dispersion of metasurface at the frequency of interest. Then, following the Butterworth filter design method, the meticulously designed metasurface, acting as lumped elements, are properly stacked to achieve a near-rectangular filtering response. Compared to the conventional designs, the proposed approach can simultaneously combine high selectivity with the theoretically widest out-of-band rejection in a considerably simple and time-efficient manner of circuit assembly, similar to electronic circuits, without extensive numerical simulations and complex structures. This dispersion synthesis approach provides exciting possibilities for high-performance metasurface design and future integrated circuits and chips.

A highly reliable and low-overhead quadruple-node-upset tolerant latch design

With the advancement of semiconductor technology and the continual reduction in the feature size of transistors within integrated circuits (ICs), ICs are becoming more and more vulnerable to soft errors induced by energetic particles in harsh radiation environments. To mitigate the impact of soft error on ICs. This paper proposes a quadruple-node-upset tolerant latch (LCQNUT), which consists of two parts: a storage module and a three-stage interception module. The storage module is composed of 12 dual-input inverters. The three-stage interception module is composed of 6 dual-input C-elements (CEs). Based on the CEs and dual-input inverters' blocking capability, the proposed LCQNUT latch can efficiently tolerate the simultaneous upset of any four internal node combinations. Simulation results indicate the proposed LCQNUT latch has the smallest power consumption, area overhead, and area-power-delay product (APDP) compared to the latches with the same soft tolerance ability (D-LATCH, HS-QNU, QNUTL). It has moderate sensitivity to process, voltage, and temperature (PVT).

Automated void detection in high resolution x-ray printed circuit boards (PCBs) images with deep segmentation neural network

Defect detection and quantification on printed circuit board (PCB) assemblies are crucial for ensuring the quality of electronic products. X-ray inspection is commonly used to detect internal defects, in which high-resolution gray-scale images are captured to reveal the internal structure, particularly the defect features, of an assembled PCB. To detect defect features, conventional computer vision techniques require hand-crafted feature filters and usually have a narrow application scope. This study introduces an automated method for detecting voids using supervised machine learning. The method employs end-to-end segmentation models to identify pixels that belong to the void and integrated circuit (IC) regions in X-ray PCB images. The segmentation results are then used to compute the percentage of voids within each IC, which is a key measure of the quality of the inspected PCB. Accurate predictions with an intersection over union of over 0.95 have achieved. A challenge in this development is the large size of the images, which can reach to millions of pixels, and the small scale of defect features. Training a deep segmentation model for large-scale images using conventional methods requires a lot of memory. Downscaling high-resolution images result in the loss of defect features. In this study, a unique training method utilizing the local nature of the defects is proposed, which reduces memory consumption and speeds up the training process. Additionally, to overcome the limited training data, various augmentation methods are applied and transfer learning is employed to construct segmentation models for different types of PCBs.

Role of Artificial Intelligence in VLSI Design: A Review

Abstract:: Artificial intelligence (AI) related technologies are being employed more and more in a range of industries to increase automation and improve productivity. The increasing volumes of data and advancements in high-performance computing have led to a sharp increase in the application of these methods in recent years. AI technology has been widely applied in the field of hardware design, notably in the design of digital and analogue integrated circuits (ICs), to address challenges such as rising networked devices, aggressive time-to-market, and everincreasing design complexity. However, very little attention has been paid to the issues and problems related to the design of integrated circuits. The authors of this article review the stateof- the-art in AI for circuit design and optimization. AI offers knowledge-based technologies that give challenges a foundation and structure. A technology known as AI makes it possible for machines to mimic human behavior. Data in all formats, including unstructured, semistructured, and structured, can be processed by AI. It is crucial to incorporate all of the features and levels of the many CAD programmes into a single, cohesive environment for creation, as was mentioned in the section that came before this one. Consequently, the application of AI automation helps to enhance the effectiveness and efficiency of CAD's performance.

High-response humidity sensor based on silicon microbridge with edge-constrained sandwich sensing structure

Silicon microbridge structures have attracted the attention of researchers in humidity sensing area owing to their small size and ease of integration with the integrated circuit (IC). However, the preparation of silicon microbridge humidity sensors with high response are still a challenge. This paper proposed a silicon microbridge humidity sensor based on an edge-constrained sandwich sensing structure, in which a graphene oxide core layer with small area was covered on the surface of the silicon bridge by a larger area of Nafion film. Due to the constraint of the peripheral edge, the swelling deformations of this sandwich structure in the vertical direction were effectively magnified during humidity detection. Hence, the proposed humidity sensor exhibited a higher humidity sensitivity (109.97 µV/%RH) compared to the silicon microbridge sensors with general sandwich sensing structure or monolayer sensing film. Meanwhile, the novel sensor also demonstrated a small humidity hysteresis and good linearity in humidity range of 11.3–97.3%.

Carbon-silicon based hybrid quantum dot short wave infrared photodetector

Recently infrared photodetectors based on low-dimensional semiconductors have developed rapidly. However, due to its poor light absorption and incompatibility with traditional silicon-based readout circuit processes, the sensitivity and integration of such photodetectors are limited. In this work, we proposes a 64 × 64 quantum dot short-wavelength infrared (SWIR) photodetector composed of carbon nanotube thin film transistor (CNT TFT) and silicon-based ROIC. CNT TFT's gate is constructed by PbS colloidal quantum dots (PbS CQDs) which improve the absorption rate of infrared light. The generated photovoltage is amplified and converted in situ by CNT TFT. Notably, under infrared radiation of 1300 nm, the noise equivalent current reach up to 1.25*10−13A/Hz1/2. At a drain-source bias (Vds)= -0.1 V. The device exhibits detectivity of 5.6*1013 Jones and a fast response of 0.57 ms. The silicon-based ROIC is implemented by CMOS 0.18um process, with a power supply voltage of 1.8 V. It mainly includes a programmable integrator, a sampling and holding circuit, and a 10bit/2.5 MHz successive approximation analog-to-digital converter (SAR ADC). The programmable integrator has four levels of integral gain to meet the application requirements of different infrared light intensities. The experiment results show that the imaging function of the overall photodetector is correct, laying the foundation for the development of carbon-silicon based heterojunction integrated photodetector in the future.